The present invention relates to a semiconductor memory device and more particularly to a power-down mode control circuit for controlling the internal operation clocks in order to enter into a power-down mode during an active mode operation.
In general, a semiconductor memory device is designed to achieve high cell capacity, high operational speed, and low power consumption. A power-down mode is available in a semiconductor memory device to minimize the amount of driving current consumed when data access operations are not performed.
FIG. 1 is a timing diagram showing the conventional entry and exit timing of a power-down mode in a conventional semiconductor memory device.
In a conventional semiconductor memory device of FIG. 1, a clock enable signal CKE is changed from a high level to a low level when entering into a power-down mode, and the clock enable signal CKE is changed from a low level to a high level when exiting from the power-down mode.
The clock enable signal CKE interfaces with the external chipset even during a power-down mode of the semiconductor memory device and serves as a reference signal for determining whether to transmit the clock signal CLK (which is inputted from the external chipset) to the semiconductor memory's core region.
FIG. 2 is a timing diagram explaining the conventional way of entering into a power-down mode from a read operation in a conventional semiconductor memory device. FIG. 3 is a timing diagram explaining the conventional way of entering into a power-down mode from a write operation in a conventional semiconductor memory device. FIG. 4 is a timing diagram explaining the conventional way of entering into a power-down mode from a write operation with an auto-precharge command in a conventional semiconductor memory device.
It is noted that the operations for entering into a power-down mode from a read operation with an auto-precharge command (ie., read with autoprecharge) is same as the operations for entering into a power-down mode from a read operation, and thus the description for the above will not be made in a redundant manner.
Referring to FIGS. 2-4, ‘DQ_BL8’ is a data signal inputted when a burst length is 8, and ‘DQ_BL4’ is a data signal inputted when a burst length is 4. Further, ‘RL’ denotes a read latency; ‘WL’ denotes a write latency; and ‘tRDPDEN’ denotes a time between the start of read operation and the point of entry to the power-down mode. ‘tWRPDEN’ denotes the time between the start of a write operation and the point of entry to the power-down mode; ‘tWTR’ (i.e., a write to read command delay) denotes the time required for processing the inputted data (that is, the time needed for the write data processing); and ‘tWR’ denotes a write recovery time.
Conventionally as shown in FIGS. 2-4, when a power-down mode entry command is received while an active mode operation (i.e., a read operation, a read operation with an auto-precharge command, a write operation, or a write operation with an auto-precharge command) is in progress, the entry to the power-down mode is implemented after completing the active mode operation in progress.
That is, when a conventional semiconductor memory device enters into a power-down mode, all input buffers are turned off to decrease current consumption, and all internally operating clocks are also disabled, except the clocks associated with the active mode operation in progress. If the power-down mode entry command is received during an active mode operation, the clock(s) associated with the active mode operation in progress is not disabled in order to complete the active mode operation in progress.
Therefore, when the power-down mode entry command is received in a conventional memory device during an active mode, the internally operating clocks are selectively controlled in order to enter into a power-down mode, and the control is conducted using the control signals outputted from a circuit provided in the semiconductor memory device that generates the clock enable signals. In other words, when the conventional semiconductor memory device enters into a power-down mode, all clocks operating in the conventional memory device are disabled using the various types of clock enable signals cke_com, cke_clk, and cke_com1, all of which are outputted from a power-down mode control circuit.
Here, the clock enable signal cke_com is the signal for turning off the commands and the address buffers; the clock enable signal cke_clk is the signal for disabling internally operating clocks excluding those employed in the active mode operation; and the clock enable signal cke_com1 is the signal for disabling the internally operating clocks employed in the active mode operation and a delay locked loop (DLL) clock.
Further, in a conventional semiconductor memory device as shown in FIG. 5, when the power-down mode entry command is received during an active mode operation, the clock enable signal cke_com1 is maintained in a disabled state (that is, in a low level), and then the clock enable signal cke_com1 is changed to an enabled state (that is, in a high level) after completing the active mode operation to disable the internally operating clocks operated in the active mode operation and in association with the DLL.
Hence, a conventional power-down mode control circuit in a semiconductor memory device requires a control circuit (not shown) for outputting the clock enable signal cke_com1 of high level at the time of completing the active mode operation. The conventional control circuit for outputting the clock enable signal cke_com1 receives signals including a CAS pulse signal casp6 of a high level pulse outputted during read and write operations; a CAS latency CL for a read operation; a write latency WL for a write operation; and a write recovery time tWR for auto-precharge.
The conventional control circuit uses the above-mentioned signals (i.e., the CAS pulse signal casp6, the CAS latency CL, the write latency WL, and the write recovery time tWR) to output a control signal cke_ctrl by counting each of them starting from each command to know the time at which the active mode operation is complete. Accordingly, a conventional semiconductor memory device enables the clock enable signal cke_com1 at the time of completing the active mode operation using the control signal cke_ctrl outputted from the control circuit.
Therefore, the control circuit is required to count each of the CAS pulse signal casp6, the CAS latency CL, the write latency WL, and the write recovery time tWR since the beginning of each command.
To perform such counting operations, the control circuit requires: a plurality of D flip-flops for counting the CAS latency CL; a plurality of D flip-flops for counting the write latency WL; and a plurality of D flip-flops for counting the write recovery time tWR; and multiplexers for the respective D flip-flops, all of which could result in several tens of D flip-flops depending on the specification for the CAS latency CL, write latency WL, and the write recovery time tWR.
Because a conventional memory device requires a plurality of D flip-flops and a plurality of multiplexers in the control circuit, a wide area must be set aside to devise the power-down mode control circuit having the above-mentioned control circuit utilizing the D flip-flops.
Further, this increases the current consumption to drive the D flip-flops and multiplexers in a conventional power-down mode control circuit.